Find chiplet integration technology in the simplest scheme

A research team consisting of Specially Appointed Professor Yoichiro Kurita (Future Interdisciplinary Science and Technology Laboratory, Institute of Innovative Research, Tokyo Institute of Technology) and a joint research company has developed a chiplet integration technology using a technology called “”. Pillar-Suspended Bridge (PSB)” This technology meets the broadband chip-to-chip communication and scalable chiplet integration requirements for future large-scale chiplet integration with minimal configuration and manufacturing processes.

It features a silicon bridge connection structure with fine “micro-pillars” that realize broadband communication between chips and a manufacturing process called “all chip last”. The structure and process provide the chiplet integration requirements in its simplest form. This technology is expected to accelerate the evolution of semiconductor integrated circuit system technology in the future and replace the miniaturization, which is expected to slow down.

This research was conducted jointly with Aoi Electronics Co., Ltd. and four other companies prior to the Chiplet Integration Platform Consortium (described later), which will be launched on October 1. Detailed results will be presented at the international conference IMAPS 2022 to be held in 2022. It will be held in Boston, USA from October 3rd.

Since its invention in the mid-20th century, semiconductor integrated circuits have become the world’s digital transformers thanks to Moore’s Law, which increases performance, reduces power consumption, and reduces costs through device miniaturization and increased integration. It is the driving force behind the formation. However, in recent years, the size of semiconductor circuits has been miniaturized to several nanometers. Due to the physical limitations imposed by the size of the atoms that make up semiconductors, the industry now sees the end of this law.

On the other hand, chiplet integration technology (Fig. 1) is attracting attention as a new evolutionary path to achieve scale-up of integration, performance improvement, and power consumption reduction instead of miniaturization. It consists of assembling a major system from a collection of integrated circuit chips that are more tightly coupled than traditional semiconductor packaging technology. It goes beyond the physical/manufacturing technological dimension of semiconductor wafers and chips to integrate various functions and structures on a large scale. This makes it possible to improve performance through heterogeneous integration and integration scalability, which were not possible with conventional semiconductor integrated circuit technology.

Integration techniques using silicon interposers and polymer-based Redistribution Layer (RDL) interposers (also known as RDL-first/Chip-last Fan-Out) have been developed and implemented as platform techniques for chiplet integration, Large-scale integration has its limits. Depends on wafer size and manufacturing technology. On the other hand, for large-scale integration, a technology for locally placing high-density wiring chips called a silicon bridge is being developed. However, the complexity of the structure and manufacturing process, as well as the high manufacturing precision required for increased integration, pose challenges.

reaserch result

Researchers have devised the Pillar Suspension Bridge (PSB) technology in the simplest scheme as a chiplet integration structure/process and built a proof-of-concept prototype to prove its feasibility. Figures 1 and 2 show the PSB bridge connection structure. Only pillar-shaped metal called “micro pillar” is interposed in the connection part between the chiplet and the silicon bridge. The chiplet is sealed with mold resin along with the bridge, and is connected to the external electrode by a “tall pillar” that penetrates the mold on the silicon bridge side.

This structure makes it possible to improve the chip-to-chip connection density and electrical characteristics by minimizing the chiplet/bridge interconnect elements, and to improve the high-frequency characteristics and heat dissipation performance of the external connection wiring. Other advantages include the ability to select the type of bridge wiring, the ability to scale up the integration (Known Good Bridge) without yield problems, and the ability to extend the size and manufacturing unit of the integrated module to large panels.

This structure is achieved by (1) the high bonding accuracy of the all-chip last process and the reduction of “die shift” (a phenomenon in which the chip moves during mold sealing) during the manufacturing process, and (2) the matching linear bonding process. Expansion (Coefficient of Thermal Expansion: CTE).

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Although Moore’s Law is expected to slow down the scaling of semiconductor integrated circuits, chiplet integration technology could become a new evolutionary path for improving system performance. This platform technology is expected to have a great impact on human society in the long term, and the emergence of a huge industry that accompanies it. This technology and its elemental technologies and applications are expected to contribute to these trends.

future development

Researchers plan to increase interconnect density and scale up integration, develop high-performance bridge wiring technology and global wiring integration technology, verify reliability, and validate system applications.

In addition, we will establish a chiplet integration platform consortium for the purpose of research and development in the value chain from manufacturing technology and elemental technology to application and industrialization, targeting chiplet integration platform technology in general, including this research.

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